1. Field of the Invention
The present invention relates to a battery state monitoring circuit and a battery device that detect a voltage and an abnormality of a secondary battery, and more particularly, to a battery state monitoring circuit and a battery device that are capable of controlling charge by a charger even if a secondary battery voltage drops to around 0 V.
2. Description of the Related Art
A battery device is provided with a function of allowing/inhibiting the charge to a secondary battery when a charger is connected thereto in a state where a voltage of the secondary battery extremely drops to around 0 V (see, for example, Japanese Patent Application Laid-open No. 2000-308266). Hereinafter, such a function is referred to as function of allowing/inhibiting 0 V charge.
FIG. 3 illustrates a circuit diagram of a battery device provided with a conventional battery state monitoring circuit. The battery device provided with the conventional battery state monitoring circuit includes a secondary battery 1, a charge/discharge control circuit 2 for monitoring a voltage of the secondary battery 1, a switch circuit 3 for controlling the charge and discharge of the secondary battery 1, external terminals 4 and 5 between which a charger 8 or a load 9 is to be connected, and a charge switch drive circuit 7 for outputting a control signal to a charge switch 11. The charge switch drive circuit 7 includes a level shifter circuit 15 that is connected to an output terminal of the charge/discharge control circuit 2, a P-type metal oxide semiconductor (PMOS) transistor 16, an N-type metal oxide semiconductor (NMOS) transistor 17, a resistor 18, an inverter (INV) circuit 26, a NOR circuit 25, a PMOS transistor 20, and an NMOS transistor 21. The PMOS transistor 16, the NMOS transistor 17, and the resistor 18 together form a voltage detection circuit for detecting a negative terminal voltage of the secondary battery 1. The PMOS transistor 20 and the NMOS transistor 21 together form an output circuit of the charge switch drive circuit 7. The battery device of FIG. 3 has a function of allowing the 0 V charge.
The battery device described above functions to allow the 0 V charge through the following operations.
The charge/discharge control circuit 2 operates with the voltage of the secondary battery 1 to monitor the voltage of the secondary battery 1. If the voltage of the secondary battery 1 increases to an overcharge voltage or higher, the charge/discharge control circuit 2 outputs a signal of Low to the charge switch drive circuit 7. On the other hand, if the voltage of the secondary battery 1 falls below the overcharge voltage, the charge/discharge control circuit 2 outputs a signal of High to the charge switch drive circuit 7. The charge switch drive circuit 7 operates with an inter-external terminal voltage between the external terminals 4 and 5. The level shifter circuit 15 converts the signal of the charge/discharge control circuit 2 into the inter-external terminal voltage. Each of the PMOS transistor 16 and the NMOS transistor 17 has a gate connected to a negative terminal of the secondary battery 1. In a state where the secondary battery 1 has a sufficient voltage, the PMOS transistor 16 is turned ON to output a signal of Low to the NOR circuit 25. On the other hand, if the voltage of the secondary battery 1 falls to around 0 V, the NMOS transistor 17 is turned ON to output a signal of High to the NOR circuit 25.
The NOR circuit 25 outputs a signal of Low when at least one of its input signals is High. Accordingly, a voltage of an output terminal 13 becomes High to turn ON the charge switch 11 so that the charge may be allowed. On the other hand, the NOR circuit 25 outputs a signal of High when both of its input signals are Low. Accordingly, the voltage of the output terminal 13 becomes Low to turn OFF the charge switch 11 so that the charge may be inhibited. Therefore, even if the voltage of the secondary battery 1 falls to around 0 V, the charge switch drive circuit 7 allows the charge. In other words, the battery device functions to allow the 0 V charge.
Meanwhile, in the above-mentioned charge switch drive circuit 7, each of the gates of the PMOS transistor 16 and the NMOS transistor 17 forming the voltage detection circuit is connected to the negative terminal of the secondary battery 1, which leads to the following drawback.
At what voltage the voltage detection circuit removes inhibition on the charge to allow the charge to the secondary battery 1 is determined based on a threshold voltage of the PMOS transistor 16. Further, there is a fluctuation in threshold voltage of the PMOS transistor 16. The output signal of the charge/discharge control circuit 2 is indefinite until the voltage of the secondary battery 1 becomes equal to or higher than a minimum operating voltage of the charge/discharge control circuit 2. Therefore, there is a fear that the output signal of the charge/discharge control circuit 2 may be indefinite when the voltage detection circuit removes inhibition on the charge to allow the charge. If the output signal of the charge/discharge control circuit 2 corresponds to a signal of inhibiting the charge, the charge to the secondary battery 1 is inhibited. As a result, such a malfunction occurs that the inhibition of the charge to the secondary battery 1 cannot be canceled any more once the charge thereto is inhibited.